The present invention relates to the field of multi-chip modules, and more particularly to triangularly assigning pins used for diagonal interconnections to minimize the length of the longest diagonal interconnection in a multi-chip module.
Circuit boards with multiple Very Large Scale Integrated (VLSI) circuit chips are called Multi-Chip Modules (MCM). Performance of an MCM may be affected at least in part by the length of interconnections between chips. The longer the distance of an interconnection between chips, the greater the time for a signal to be transmitted from one chip to another chip. Hence, the longer the distance of an interconnection between chips, the lower the processing speed of the MCM.
In an MCM, each chip may be interconnected with another adjacent or diagonal chip within the substrate. The interconnection between adjacent chips may commonly be referred to as an xe2x80x9corthogonalxe2x80x9d interconnection. The interconnection between chips diagonal to one another may commonly be referred to as a xe2x80x9cdiagonalxe2x80x9d interconnection. Typically, the orthogonal interconnections are shorter in distance than the diagonal interconnections. In fact, the diagonal interconnections may be forty percent (40%) longer than orthogonal interconnections.
If the length of the longest diagonal interconnection can be made with a length no longer than the length of the longest orthogonal interconnection, the performance of the MCM may be improved. That is, by minimizing the length of the longest diagonal interconnection to be substantially the same length as the length of the longest orthogonal interconnection, the performance of the MCM may be improved by improving the processing speed of the MCM.
It would therefore be desirable to minimize the length of the longest diagonal interconnection to be substantially the same length as the length of the longest orthogonal interconnection in a multi-chip module in order to improve the performance of the multi-chip module.
The problems outlined above may at least in part be solved in some embodiments by assigning pins used for diagonal interconnections to form a triangular pattern thereby allowing the length of the longest diagonal interconnection to be substantially the same length as the length of the longest orthogonal interconnection. Further, by assigning pins used for diagonal interconnections to form a triangular pattern, the length of the longest diagonal interconnection may be substantially the same length as the length of the second longest diagonal interconnection.
In one embodiment of the present invention, a multiple chip module may comprise a first chip, a second chip located adjacent to the first chip and a third chip located diagonally to the first chip. The first and the second chip are interconnected by one or more orthogonal interconnections. The first and the third chip are interconnected by one or more diagonal interconnections. Since the one or more diagonal interconnections between the first chip and the third chip are interconnected between a set of pins on each chip that form a triangular pattern, the longest diagonal interconnection is substantially the same length as the length of the longest orthogonal interconnection. Further, since the one or more diagonal interconnections between the first chip and the third chip are interconnected between a set of pins on each chip that form a triangular pattern, the longest diagonal interconnection is substantially the same length as the length of the second longest diagonal interconnection.
A method for identifying pin locations to be used for diagonal interconnections in a multiple chip module may comprise the step of calculating the lengths of a plurality of orthogonal interconnections from pin locations on a particular chip to corresponding pin locations on an adjacent chip in a multi-chip module. Furthermore, the lengths of a plurality of diagonal interconnections from pin locations on a particular chip to corresponding pin locations on a diagonal chip may be calculated.
A threshold value may then be received from a user. The threshold value may indicate a maximum diagonal interconnection distance between a pin in a first chip and a corresponding pin in a second chip where the second chip is diagonal to the first chip. The threshold value received may be less than or equal to the longest orthogonal distance thereby ensuring that the longest diagonal interconnection may be substantially the same length as the longest orthogonal interconnection. Furthermore, since the threshold value received may be less than or equal to the longest orthogonal distance, the length of the longest diagonal interconnection may be substantially the same length as the second longest diagonal interconnection.
A first number, e.g., sixteen, of available pin positions in a chip associated with diagonal interconnection distances at or below the threshold value may be tagged with a first value, e.g., number xe2x80x9c1.xe2x80x9d That is, a first number, e.g., sixteen, of pin positions not reserved for non-connecting purposes that are associated with diagonal interconnection distances at or below the threshold value may be tagged with a first value, e.g., number xe2x80x9c1.xe2x80x9d The first number of pin positions tagged with the first value may be the pin positions in a chip whose lengths for diagonal interconnections with corresponding pin positions in a diagonal chip are at or below the threshold value.
The remaining available pin positions may be tagged with a second value, e.g., number xe2x80x9c0.xe2x80x9d That is, the remaining number of pin positions reserved for non-connecting purposes may be tagged with a second value, e.g., number xe2x80x9c0.xe2x80x9d
A determination may then be made as to whether the first number, e.g., sixteen, of pins tagged with a first value is an appropriate number of pin locations to be used for diagonal interconnections. That is, a determination may be made as to whether the first number of pins tagged with a first value is not too high or too low of a number of pin locations to be used for diagonal interconnections. If the first number, e.g., sixteen, of pins tagged is an appropriate number of pin locations to be used for diagonal interconnections, then the pin positions marked with a first value may be used for diagonal interconnections. The pattern formed by the set of pins used for diagonal interconnections may appear to form a triangular pattern. Further, at least a portion of the pin positions marked with a second value may be used for orthogonal interconnections.
If the first number, e.g., sixteen, of pins tagged is not an appropriate number of pin locations to be used for diagonal interconnections, then an updated threshold value may be received from the user. An updated threshold value may be a value that is greater than or less than the previously used threshold value. Upon receiving the updated threshold value, the number of available pin positions in a chip associated with distances at or below the updated threshold value may be tagged with a first value, e.g., number xe2x80x9c1xe2x80x9d, as discussed above.
The foregoing has outlined rather broadly the features and technical advantages of one or more embodiments of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.